This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-254553, filed Sep. 8, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a voltage generating/transferring circuit and, more particularly, to a voltage generating/transferring circuit used for an EEPROM of NAND cell type, NOR cell type, DINOR cell type, or AND cell type.
As is well known, a nonvolatile semiconductor memory represented by an EEPROM must generate a boosted voltage VPP higher than a power supply voltage Vcc in normal operation, e.g., in programming. This boosted voltage VPP is generated by a boosted voltage generating/transferring circuit formed in a memory chip, and transferred to a word line.
In order to generate, transfer, and charge/discharge the boosted voltage VPP, the boosted voltage generating/transferring circuit is formed from a high breakdown voltage type MOS transistor which does not break down even upon application of the boosted voltage VPP.
In the high breakdown voltage type MOS transistor, the thickness and size of a gate insulating film are set to different values from those in a low breakdown voltage type MOS transistor which operates at the power supply voltage Vcc (in general, the gate insulating film of the high breakdown voltage type MOS transistor is thicker than that of the low breakdown voltage type MOS transistor).
Hence, the high breakdown voltage type MOS transistor cannot be manufactured directly using the manufacturing process for the low breakdown voltage type MOS transistor. Manufacturing the high breakdown voltage type MOS transistor requires its own process. This increases the number of steps up to completion of a memory chip, and increases the manufacturing cost.
As the number of types (e.g., N- and P-channel types) of high breakdown voltage type MOS transistors increases, the number of steps of manufacturing process for high breakdown voltage type MOS transistors also increases. To reduce the manufacturing cost, it is desirable to minimize the number of types of high breakdown voltage type MOS transistors and decrease the number of steps up to completion of a memory chip.
For this purpose, a conventional boosted voltage generating/transferring circuit is formed from only high breakdown voltage type N-channel MOS transistors.
FIG. 1 shows an example of the conventional boosted voltage generating/transferring circuit.
In the conventional circuit, high breakdown voltage type MOS transistors QN1, . . . , QN3, QN5, and QN6 for receiving the boosted voltage VPP are of N-channel type.
The high breakdown voltage type MOS transistors QN1, . . . , QN3 are series-connected to each other. One terminal of the MOS transistor QN1 receives the boosted voltage VPP, whereas one terminal of the MOS transistor QN3 is connected to the gate of the MOS transistor QN6. The MOS transistor QN6 transfers the boosted voltage VPP to a word line.
One terminal of the MOS transistor QN5 receives an input signal IN, its other terminal is connected to the gates of the MOS transistors QN1 and QN6, and its gate receives the power supply voltage Vcc. The gate and drain of each of the MOS transistors QN2 and QN3 are connected to each other. Each of these nodes is connected to one terminal of a corresponding one of capacitors C1 and C2. The MOS transistors QN2 and QN3 and the capacitors C1 and C2 constitute boost units.
Note that one boost unit is surrounded by a dotted line (represented by ★).
A NAND circuit NA1 receives control signals RING and PUMP. An output signal from the NAND circuit NA1 is supplied to the other terminal of the capacitor C1 via an inverter circuit I1, and to the other terminal of the capacitor C2 via inverter circuits I2 and I3.
In this boosted voltage generating/transferring circuit, the boost unit makes the boosted voltage VPP and an output voltage VOUT equal to each other. That is, the boost unit generates a voltage equal to or higher than VPP+Vtn (Vtn is the threshold voltage of the high breakdown voltage type N-channel MOS transistor), and applies this voltage to the gate (node N3) of the high breakdown voltage type MOS transistor QN6. Then, the high breakdown voltage type MOS transistor QN6 can transfer the boosted voltage VPP without any threshold drop (phenomenon in which the transfer potential drops by a threshold value).
If, however, the boosting ability of the boost unit is insufficient, i.e., the voltage of the node N3 is not boosted to VPP+Vtn or more, the output voltage VOUT becomes lower than VPP by the difference between the voltage of the node N3 and VPP+Vtn. As a result, e.g., programming operation fails.
In recent years, the power supply voltage Vcc is decreasing in the EEPROM in order to reduce the power consumption. As the boosting ability of the boost unit in the circuit of FIG. 1 increases with increasing power supply voltage Vcc, a decrease in the power supply voltage Vcc further decreases the boosting ability of the boost unit.
The boosted voltage generating/transferring circuit in FIG. 1 requires development of a technique capable of transferring the boosted voltage VPP without decreasing the boosting ability of the boost unit and causing any threshold drop even if the power supply voltage Vcc is low.
As described above, in the conventional boosted voltage generating/transferring circuit, any decrease in the power supply voltage Vcc decreases the boosting ability of the boost unit for applying a voltage to the gate of a high breakdown voltage type MOS transistor for transferring the boosted voltage VPP. Thus, an excessively low power supply voltage Vcc makes it impossible to transfer the boosted voltage VPP.
It is an object of the present invention to provide a voltage generating/transferring circuit capable of enhancing the boosting ability of a boost unit for generating a voltage to be applied to the gate of a high breakdown voltage type MOS transistor for transferring, e.g., a boosted voltage VPP, and capable of transferring the boosted voltage VPP even if the power supply voltage is low.
A voltage generating/transferring circuit according to the present invention comprises a boost unit group including a plurality of boost units series-connected between an input node and an output node, and a first transistor connected between the input node and a node for receiving a first voltage. Each boost unit has input and output portions, and includes a second transistor having a gate and a drain connected to the input portion and a source connected to the output portion, and a capacitor connected to the input portion. The gate of the first transistor is connected to the input portion of one of the boost units.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.